This invention relates to a semiconductor integrated circuit device and to a process for manufacturing the same; and, in particular, the invention relates to a process which can effectively be applied to a semiconductor integrated circuit device comprising a step for flattening a surface using CMP (Chemical Mechanical Polishing).
In semiconductor integrated circuit devices, such as a DRAM (Dynamic Random Access Memory), demand has been increasing in recent years for finer detail and a higher degree of integration. Due to the demand for greater detail in semiconductor integrated circuit devices, laminated structures in multilayer interconnections are unavoidable, but if a multilayer structure is used, imperfections are formed on the surface of the upper layer reflecting the imperfections in the substrate. If photolithography is performed when imperfections are present on the surface, sufficient tolerance of focal depth cannot be obtained in the exposure step, and this leads to poor resolution. Therefore, the surface is flattened using CMP in order to improve the photolithography of components formed on the surface.
The CMP technique is used also to form isolation regions. In the LOCOS (Local Oxidation of Silicon) technique which was frequently used in the past, it is difficult to achieve more than a certain amount of detail due to the presence of a bird's beak. Thus, a shallow groove is formed on Ia main surface of the semiconductor substrate; this groove is filled with a silicon oxide film; and the silicon oxide in the regions outside the groove are removed by CMP to form a shallow groove isolation. With a shallow groove isolation, the periphery of the isolation region is sharply defined, so the periphery can also be used effectively as an element part, so that it is easier to achieve finer detail.
However, when the CMP technique is used for polishing it is impossible to completely remove surface imperfections. When there are Imperfections on the polishing surface, a history of imperfections remains on the polishing surface to some extent. Further, if parts which are easily polished and parts which are difficult to polish are both present on the polishing surface, dishing (polishing depressions) tends to occur in the part which is easy to polish. Due to the nature of polishing in the CMP method, this history of imperfections or dishing is particularly significant when the imperfections or parts which are easy to polish have a large area. Specifically, in polishing by the CMP method, although small Imperfections can be flattened relatively well, undulations (global undulations) remain over a large area when a large pattern (usually of the order of several μm or more) is repeated, for example, and so it is difficult to flatten the surface completely.
However, a method has been proposed where a dummy pattern is disposed in regions where there are large patterns or where there is a wide pattern interval. In this method, the pattern interval is decreased due to the dummy pattern, so that the aforesaid wide area (global) dishing or undulations are suppressed. For example, in Japanese Unexamined Patent Publication No. Hei 10-335333 (1998) (Koho) (U.S. Ser. No. 09/050,416, 31 Mar. 1998), a technique is disclosed wherein a dummy pattern is disposed in a region with a wide pattern interval to improve the flatness of the surface of an insulating film which fills the pattern.